I have started learning about verification and UVM recently and wish to test a 16-bit pipelined processor that I made using Verilog. I want to know how to approach the verification of the processor. The processor takes its instruction from a .txt file that has the instruction saved in it. So should I have a driver randomly fill the instruction text file with instructions and run it on the DUT and check coverage or Is there another way to approach a processor verification?
In reply to ShubhamL:
Having instructions in a txt-file is not a good solution, because it does not allow to execute instructions and series of instructions in random order.
In reply to chr_sue:
Can we not randomize the instructions and write those instructions to a text file and pass the text file to the DUT?
In reply to ShubhamL:
Yes you Can do it, but do you want to do this. It is an additional step you do not Need.