In reply to ben@SystemVerilog.us:
Thanks for the reply. I tried your solution but couldn’t detect any change.
I am not sure if that is the problem, because data_rd is a one cycle pulse. Also it arrives once every 160 cycles. So I am expecting it to trigger only once every 160 cycles.
waveform is like :
cycle:0: first data_rd pulse, data = 7
cycle:160: second data_rd pulse, data = 15 → assertion success
cycle:320: third data_rd pulse, data = 7
cycle:480: fourth data_rd pulse, data = 8 → no sign of assertion trigger
Also there was a failure case in between and assertion shown failed.
Assertion detects every failure but is not showing every success in waveform. Am I missing any detail about the $past construct? Did I miss something from your reply?