$past in Systemverilog Assertions

In reply to Tobi:

Each attempt is separate from others.
What I see wrong is that from time 0, $past(d, n) where n < 161 is the default value of d.
2 solutions:


// better
always @(posedge clk count <= count + 1'b1;

assert property (@(posedge clk) disable iff(rst) 
count > 160 ##0 ($rose(data_rd) && (data[3:0] !=7)) |-> $past((data[3:0]==7),160));


// Too many nonvacuous attempts 
assert property (@(posedge clk) disable iff(rst) 
##161 ($rose(data_rd) && (data[3:0] !=7)) |-> $past((data[3:0]==7),160));
 

Ben Cohen
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