Passing $test$plusargs into sequence item

SystemVerilog
, ,
1

Hi,

can anyone help me how to get $test$plusargs value into my sequence item.

my requirements is
factor=clkin*divider
factor should be range as 600mhz to 1400mhz
i want to write constraint for factor for which i need clkin freq which is generated in top tb using $test$plusargs

thanks in advance

2

In reply to kathula venkatesh:
Your question is not very clear. Are you using the UVM? (Seems like yes from your previous questions). You can use the uvm_cmdline_processor to get command line arguments from any class. But even if you are not using UVM, you can still use $test$plusargs and $value$plusargs from anywhere.

If you are using the UVM, the you use the uvm_config_db to share any value you have. But is you question really about how to write a constraint and not really an issue with $test$plusargs?

3

In reply to dave_59:

hi dave,

yes i am using UVM,my question is know how to get clock frequency which was i passed from command line in to my uvm_sequence item. i am passing clock frequency in command line using $test$plusargs mentioned inside my top tb.