Passing ref array via conditional operator to function

SystemVerilog
, ,
1

Is the following code legal?


module top;

  bit condition;
  bit arr1 [4][8];
  bit arr2 [4][8];

  int i,j;

  function automatic void some_func(ref bit arr[4][8]);
    arr*[j] = 1;
  endfunction 

  initial begin
    some_func(condition ? arr1 : arr2);
  end

endmodule

The point of the “some_func” function is to be flexible to receive either arr1 or arr2 depending on “condition”. The function will then alter the contents of whichever array it is given. However, I get a compilation error:

[i] Illegal value (condition ? arr1 : arr2) for ref formal (arr). Value must be assignable.*

What am I missing?

2

In reply to a_stod:

Expression evaluation is unidirectional and not available as the target of an assignment. What if you had

module top;
  int A = 1;
  function automatic void some_func(ref int arg);
    arg = arg + 2;
  endfunction 
  initial begin
    some_func(A + 1);
    $display(A);
  end
endmodule

You would not expect A to have the value 3, would you?.

The only operators allowed in the target of an assignment are concatenation and streaming operators.

3

So is the best way to select which array is passed to the function to use:


  initial begin
    if (condition)
      some_func(arr1);
    else
      some_func(arr2);
  end

? Or is there a more elegant way?

4

In reply to a_stod:

Depends on what your definition of “elegant” is. You could use a class

module top;
  class A;
    bit arr [4][8];
  endclass
  bit condition;
  A arr1 = new;
  A arr2 = new;
 
  int i,j;
 
  function automatic void some_func(A h);
    h.arr[i][j] = 1;
  endfunction 
 
  initial begin
    some_func(condition ? arr1 : arr2);
  end
endmodule

This looks very close to your original example code. But I’m guessing it’s very simplified from your actual code.