In reply to germanbravolopez:
Hi,
Check the this code and modify according to your requirements, based on the expected results you showed and the type of data expected_tdata_pkgis, but I have to ask are you aware that in the code using ‘+:’ you are basically overriding the lower part expected_tdata_pkg (WDW/RDW) times, I’m not sure why, maybe you could explain the type of “packaging” you what to achieve.
// Code your testbench here
// or browse Examples
typedef bit [127:0] tdata_t;
module tb;
tdata_t expected_tdata_pkg;
tdata_t tdata;
int WDW = 32, RDW = 16;
initial begin
$display ("tdata=%0h \n expected_tdata_pkg=%0h \n", tdata, expected_tdata_pkg);
tdata = 32'hcafeabcd;
$display ("tdata=%0h \n expected_tdata_pkg=%0h \n", tdata, expected_tdata_pkg);
for (int i = 0; i < (WDW/RDW); i++) begin
//for (int j = 0; j < RDW; j++) begin
expected_tdata_pkg = tdata[16*i +: 16]; // RDW
//end
$display ("----> tdata=%0h \n expected_tdata_pkg=%0h \n", tdata, expected_tdata_pkg);
end
expected_tdata_pkg = 0;
for (int i = 0; i < (WDW/RDW); i++) begin // I'm assuming you know the length or use a foreach
for (int j = 0; j < RDW; j++) begin
expected_tdata_pkg [j] = tdata[i*RDW + j];
end
$display ("++++++> tdata=%0h \n expected_tdata_pkg=%0h \n", tdata, expected_tdata_pkg);
end
end
endmodule