Passing parameterized interface to module port

SystemVerilog
3

In reply to dave_59:

Hello @Dave,

  1. Say I use this module as interface_wrapper which binds at the TB Top. And this module contains the code to set the static interface to the testbench using config_db. Example code as shown below.

module dut_wrapper(ex_if i);
 initial begin 
   uvm_config_db#(virtual ex_if)::set(null, "*", "ex_if_vif", i);
 end 
endmodule
  1. But I face the compatibility issue with respect to the uvm_config_db, because the default element in the uvm_config_db expects a default parameters for the interface, but while we pass the interface to the module we set different parameters to the interface.

So how can we pass the parameters that you use to for the interface and pass the same to the uvm_config_db #(virtual ex_if #(? ?)).

Do I need to pass that as parameter inputs to the interface wrapper module and then set in the config_db as show below ? so that the data types matches ? [Because this way was able to configure the right parameters to the interface and as well to the virtual interface defined in uvm_config_db]


module dut_wrapper#(W1, W2)(ex_if i);
 initial begin 
   uvm_config_db#(virtual ex_if#(W1, W2))::set(null, "*", "ex_if_vif", i);
 end 
endmodule

module top;
 ex_if #(7,8) i1();
 dut_wrapper DUT#(7, 8)(i1);
endmodule

Or is there any other better way for the above scenario. Any suggestion would be highly helpful.