Passing hierarchy using `define

SystemVerilog
, ,
2

In reply to gidon:

Do provide the error you see. The code below works for me.

`define PATH(i) genblock*.bb.signal

module top;

   bit clk;
   
   initial repeat(10) #5 clk++;
   initial #23 genblock[2].bb.signal = 1;
   
   for(genvar ii=0;ii<3;ii++) begin :genblock
      b bb();
   end
  
   property p(index);
      @(posedge clk) `PATH(index) ==0;
   endproperty

   for(genvar ii=0;ii<3;ii++) 
	assert property ( p(ii) );
endmodule
module b;
   bit signal;
endmodule

Your problem might be related to the fact that macros and compiler directives expand before [I]before* the compiler recognizes any SystemVerilog syntax. Attempts to redefine PATH will have no effect.