Passing Constant values to the variables?

Hi,

I am trying to pass the constant values, in sequences.
But i am not getting the values which i am passing.

class alu_5_packets extends alu_base_seq;

`uvm_object_utils(alu_5_packets)

rand bit [7:0] cin=8’d1;
rand bit [7:0] cmd=8’d19;
function new (string name = “alu_5_packets”);
super.new(name);
endfunction: new

virtual task body();
uvm_info(get_type_name(), "Executing alu 5 packet sequence", UVM_LOW) uvm_config_db#(bit[7:0])::get(null,get_full_name(),"cin", cin); uvm_config_db#(bit[7:0])::get(null,get_full_name(),"cmd", cmd); repeat(5) uvm_do_with (req, {req.cmd==cmd;
req.cin==cin;})
endtask: body

for cin it has to come 1 and for cmd it has to come 19.
But i am getting some random values.
Can you please let me know where i am doing wrong?

Thanks & Regards,
Giridhar.K

In reply to giridhar.ece:

What you are trying to do here. uvm_config_db is like a database. You should set the value before even asking the value out of a db.

uvm_config_db#(type)::set(null,"*","cin",cin_value); // from module top
uvm_config_db#(type)::set(this,"*","cin",cin_value); // from TB

In reply to Naven8:

Hi giridhar,

rand bit [7:0] cin=8’d1;
rand bit [7:0] cmd=8’d19;

the problem is here that you are initializing bt also you made it random. thats why cin and cmd are taking random values.

you can do two thing

  1. remove the rand keyword

    bit [7:0] cin=8’d1;
    bit [7:0] cmd=8’d19;

    then you will get the correct value.

  2. Or use constraint
    rand bit [7:0] cin=8’d1;
    rand bit [7:0] cmd=8’d19;

constraint c1 { cin == 1 ; }
constraint c2 { cmd == 19;}

Regards
Ashish
1117ashish@gmail.com

In reply to 1117ashish:

Hi Naven and ashish,

Thanks for your reply.
Naven now i understood why uvm_config_db used.
I have changed my code. Now i am able to pass the parameters directly.
Modified code is:

class alu_5_packets extends alu_base_seq;

`uvm_object_utils(alu_5_packets)

bit [7:0] cin=8’d1;
randc bit [7:0] cmd;
constraint cmd_typ { cmd inside {1,2,19,35,67,131};}

function new (string name = “alu_5_packets”);
super.new(name);
endfunction: new

virtual task body();
uvm_info(get_type_name(), "Executing alu 5 packet sequence", UVM_LOW) uvm_create(req)
assert(req.randomize());
for(int i =0; i<10; i++) begin
req.cmd = i8;
req.cin = (4-i
2);
`uvm_send(req)
end

endtask: body

endclass: alu_5_packets

Please let me know if any thing wrong…

And i didnt understand why the below piece of code didnt work.

`uvm_do_with (req, {req.cmd==cmd;
req.cin==cin;})

Thanks & Regards,
Giridhar.K

In reply to giridhar.ece:

Hi,

virtual task body();
uvm_info(get_type_name(), "Executing alu 5 packet sequence", UVM_LOW) for(int i =0; i<10; i++) begin uvm_do_with(req,{req.cmd==i8;req.cin==(4-i2);})
end
endtask: body

In uvm_do_with, whether we can pass the integer values like above code?
Because the above is not working.
But if i pass the values like…
`uvm_do_with(req,{req.cmd==8;req.cin==4;})
It is capturing the values 8 and 4.

Is there any way to do like below code?
for(int i =0; i<10; i++) begin
`uvm_do_with(req,{req.cmd==i8;req.cin==(4-i2);})
end

Thanks & Regards,
Giridhar.K

In reply to giridhar.ece:

Can you explain what you are expecting to see and what you are actually seeing? I see several potential issues which may or may not be correct based upon what you are attempting to accomplish.

In reply to cgales:

Hi,

I am expecting for cmd = 0,8,16,24,…,72 and cin first two clock cycles 4 and 2, afterwards any thing it ll be okay.
But I am seeing all zeros if i use `uvm_do_with(req,{req.cmd==i8;req.cin==(4-i2);}).

In reply to giridhar.ece:

Here are some things you need to look at:

  • You don’t post the base class of req. This is the sequence item being generated and passed to your driver. We would need to see the class code to make sure that you have all the randomization configured correctly.
  • Any randc constraints apply to that class and not the generated class. You would need to randomize alu_5_packets to account for the cmd_typ constraint.
  • Do not wrap any randomize() calls within an assert statement. This will cause problems.
  • Don’t use the `uvm_do_* macros.
  • Refer to the UVM Cookbook section on sequences to see how to generate sequence items correctly.

In reply to cgales:

Hi cgales,

Thankyou very much.
Your suggestions are valuable.
I will follow your suggestions.

My class code is:
class alu_base_seq extends uvm_sequence #(alu_packet);

alu_packet req;

`uvm_object_utils(alu_base_seq)

function new (string name = “alu_base_seq”);
super.new(name);
endfunction: new

task pre_body();
starting_phase.raise_objection(this, get_type_name());
`uvm_info(get_type_name(), “raise objection”, UVM_MEDIUM)
endtask: pre_body

task post_body();
starting_phase.drop_objection(this, get_type_name());
`uvm_info(get_type_name(), “drop objection”, UVM_MEDIUM)
endtask: post_body

endclass: alu_base_seq

And extended class is:
class known_10_packets extends alu_base_seq;

`uvm_object_utils(known_10_packets)

function new (string name = “known_10_packets”);
super.new(name);
endfunction: new

virtual task body();
uvm_info(get_type_name(), "Executing known_10_packets sequence", UVM_LOW) uvm_create(req)
for(int i =0; i<10; i++) begin
req.cmd = i8;
req.cin = (4-i
2);
`uvm_send(req)
end
endtask: body

endclass: known_10_packets

Thanks & Regards,
Giridhar.K

In reply to giridhar.ece:

You haven’t posted the code for alu_packet. This is the uvm_sequence_item that you are creating. Also, how do you know that what you are creating has 0’s for values? Do you print out the values somewhere?

In reply to cgales:

Hi cgales,

My alu packet is:

class alu_packet extends uvm_sequence_item;
randc bit [7:0] cmd;
rand bit cmd_val;
rand bit [7:0] cin;
rand bit [7:0] cout;
rand bit cout_val;

constraint cmd_7 { cmd inside {1,2,19,35,67,131};}

uvm_object_utils_begin(alu_packet) uvm_field_int(cmd, UVM_ALL_ON)
uvm_field_int(cmd_val, UVM_ALL_ON) uvm_field_int(cin, UVM_ALL_ON)
uvm_field_int(cout, UVM_ALL_ON) uvm_field_int(cout_val, UVM_ALL_ON)
`uvm_object_utils_end

endclass: alu_packet

I am checking in the waveform. I am not printing anywhere. But in the waveform i am checking.

Thanks & Regards,
Giridhar.K