Passing array string to vpi_handle_by_name

SystemVerilog
,
1

Hi,

This is a part of my test.sv code:

interface Bus;
   logic [7:0] sig1;
   logic [15:0] sig2;
   logic sig3;
 endinterface

 module test();
   Bus inst();
   ...
 endmodule

I have given the vpiFullName ‘test.inst.sig1’ to the vpi_handle_by_name in c++ code.

vpiHandle it1, it2, it3;

 it1 = vpi_handle_by_name("test.inst.sig1", NULL);
 func(it1, vpiBit);
 it2 = vpi_handle_by_name("test.inst.sig2", NULL);
 func(it2, vpiBit);
 it3 = vpi_handle_by_name("test.inst.sig3", NULL);
 func(it3, vpiBit);

 static void
 func(vpiHandle net, PLI_INT32 nettype)
 {
    char *name = vpi_get_str(vpiFullName, net);

    auto size = vpi_get(vpiSize, net);
    ...
 }

But I’m extracting the strings (sig1, sig2,…) from a file and storing it in an array ‘arr’. I want to pass these strings in the form of array to vpi_handle_by_name like this:

vector <std::string> arr;

 it1 = vpi_handle_by_name((PLI_BYTE8 *)(arr[0].c_str()), NULL);
 func(it1, vpiBit);
 it2 = vpi_handle_by_name((PLI_BYTE8 *)(arr[1].c_str()), NULL);
 func(it2, vpiBit);
 ...

“vpi_handle_by_name” obtains a handle for any Verilog object using the name of the object.

arr[0] and arr[1] contains “sig1” and “sig2” respectively but the name and size cannot be generated because arr[0] and arr[1] are not present in the SV module.

I don’t want to give the signal names directly like ‘test.inst.sig1’ since the name changes depending on the file. So I would like to give in the form of array with strings extracted from file.

Any suggestion would be of great help to me.