Passing arguments by reference

SystemVerilog
6

In reply to desperadorocks:

Works for me in Questa.

module top;
class C; 
   bit a[10];
   extern virtual task p(ref bit c);
endclass : C
   task C::p(ref bit c);
      #10;  
   endtask : p
   C c	=new;
   
   initial begin
      c.p(c.a[1]);
   end
endmodule : top

Can you show me a small, complete, self-contained example?