Passing arguments by reference

SystemVerilog
2

In a function, the only benefit is performance in passing large data structures like an array instead of using an inout.

In a task that consumes time, a ref can be used instead of an inout to capture value changes that occur while the task is active. Remember that an inout argument is copied into the task when it is called, and copied out when the task returns. Here is an example that I did not try, so excuse the typos.

module top;
logic A,B;
task automatic mytask(inout logic arg1, ref logic arg2);
  #0 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
  // actual arguments have been set to 0
  #5 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
  #0 arg1 = 1; arg2 = 1;
  #5 $display("%m %t arg1 %b arg2 %b",$time,arg1,arg2);
endtask
initial #1 mytask(A,B);
initial begin
       A = 'z; B ='z;
       #2 A = 0; B = 0; // after call 
       // arguments have been set to 1
       #5 $display("%m %t A %b B %b",$time,A ,B);
       #5 $display("%m %t A %b B %b",$time,A ,B);
end
endmodule

See the difference between the inout and pass by ref arguments.

Note that a class variable is a reference to a class handle already, so passing a class variable by reference rarely has any benefit.