Passing a struct when instantiating a module

SystemVerilog
, , ,
1

i have an issue when passing a structure of logic signals from a submodule to the topmodule.

i stripped the code down to minumum to only show the part resulting in the issue.

there is a .h file called ptc_structure.h, where the structure is defined:

typedef struct {
logic pWRT_PLLRESET;
logic pWRT_PLLSWITCH;
logic [2:0] pWRT_SELECT;
} st_PTC_WRT;

both, the topmodule (PTC.sv) and the submodule (P_AVSIF.sv) include the .h file above.

in the module header of the submodule (P_AVSIF.sv), i have

module P_AVSIF (
output st_PTC_WRT s_pWRT
);

and in the topmodule (PTC.sv), i have

st_PTC_WRT s_pWRT;

P_AVSIF AVSIF (
.s_pWRT (s_pWRT)
);

when running questasim, i get the error message below:

** Error: (vsim-3906) Connection type ‘struct PTC_sv_unit::st_PTC_WRT’ is incompatible with ‘struct P_AVSIF_sv_unit::st_PTC_WRT’ for port (s_pWRT): Struct/union types must match.

to me, this message looks like the definition of the structure, used to define s_pWRT is different within the two files. but fact is, that both files use the definition from ptc_structure.h, i.e. it is the same for both.

so what am i doing wrong?

2

In reply to bongo1:

By including the file in different locations, you are creating the definition within multiple compilation scopes, which makes them incompatible.

What you want to do is create a package with the structure definition, and import the package where required:

ptc_params_pkg.sv:


package ptc_params_pkg;
  typedef struct {
    logic pWRT_PLLRESET;
    logic pWRT_PLLSWITCH;
    logic [2:0] pWRT_SELECT;
  } st_PTC_WRT;
endpackage

P_AVSIF.sv:


import ptc_params_pkg::*;
module P_AVSIF (
  output st_PTC_WRT s_pWRT
);

PTC.sv:


import ptc_params_pkg::*;
P_AVSIF AVSIF (
  .s_pWRT (s_pWRT)
);