Passing a string in module port list

SystemVerilog
1

Can we pass a string in module port list? Can someone provide an example for this?

Thanks in advance,
Naven

2 
module a_module_with_a_string_port(input string port1);
   always @port1 $display("my string port is %s",port1);
endmodule

module top;
   string s;
   a_module_with_a_string_port m(s);
   initial begin
      #1 s = "hello";
      #1 s = "world";
      #1 $finish;
   end
endmodule
3

In reply to dave_59:

Thanks Dave, I have written the same code but looks like vcs is not supporting it.
Could you please point me to the section where LRM is mentioned all supported type on module ports?

4

In reply to Naven8:

A port can be a variable, and there are no restrictions on the types of variables, only on the types of nets. See 23.2.2 Port declarations.

There are restrictions on the storage classification of variables that can be connected to a port (no automatics, no elements of dynamically sized arrays or members of classes, but no restrictions on the types. See the end of section 6.21 Scope and lifetime.