is it possible to pass queue of real numbers from UVM to SystemC using UVM Connect?
i have declared queue of real type in UVM packet class
class packet extends uvm_sequence_item; `uvm_object_utils(packet)
real beta = 0.01;
real D[];
real Y[];
function new(string name=“”);
super.new(name);
endfunction
virtual function void do_pack(uvm_packer packer); // pack operation for transaction
super.do_pack(packer);
uvm_pack_real(beta) uvm_pack_queue(D)
`uvm_pack_queue(Y)
endfunction
virtual function void do_unpack(uvm_packer packer); // unpacking operation
super.do_unpack(packer);
`uvm_unpack_real(beta)
`uvm_unpack_queue(D)
`uvm_unpack_queue(Y)
endfunction
endclass
in the SystemC side my converter is as follows
class packet
{
public:
double beta; // CONVERGENCE RATE
vector D;
vector Y;
};
// converter
template <>
struct uvmc_converter {
static void do_pack (const packet &t, uvmc_packer &packer) { // packing operation
// cout << t.Y << endl;
packer << t.beta << t.D << t.Y ;
}
static void do_unpack(packet &t, uvmc_packer &packer) { // unpacking operation
packer >> t.beta >> t.D >> t.Y ;
}
};
when i am trying to print the value of element in queue, i am getting the integer values but expected is a real value.
i want to know pass a queue of real numbers from UVM to SystemC?
The problem is that the `uvm_un/pack_queue macros assume that elements of the queue are integral types. I suggest you learn what the macro expands to and insert a call to $realtobits/$bitstoreal where appropriate.
From UVMC 2.2 /examples/field_types
Supported Data Types
The following types are supported by UVMC for packing and unpacking via the streaming operators.
SV |---- SC
longint ---- long long
int |---- int
shortint |---- short
byte | --- char
bit |---- bool
longint unsigned |---- unsigned long long
int unsigned |---- unsigned int
shortint unsigned | --- unsigned short
byte unsigned |---- unsigned char
bit unsigned |---- bool
shortreal |---- float
real |---- double
string |---- string
time | --- sc_time
T |---- T
T arr[N] |---- T arr[N];
T q[$] |---- vector<T>
T da[] |---- list<T>
T aa[KEY] | --- map<KEY,T>
sc_bit |---- sc_bit
sc_logic |---- sc_logic
sc_lv [L:R] |---- sc_lv<N>
sc_bv [L:R] |---- sc_bv<N>
bit [N-1:0] |---- sc_int<N>
bit [N-1:0] |---- sc_uint<N>
bit [N-1:0] |---- sc_bigint<N>
bit [N-1:0] |- -- sc_biguint<N>
In UVM side i have used real D[$], to declare queue of real numbers. and on SystemC vector.
For packing i am using uvm_pack_queue an unpacking uvm_unpack_queue.
When i print it in UVM side it prints the correct values, but after packing and unpacking, on SystemC side it prints the integral value of the real number.
Same is true, when i pass queue of real numbers from SystemC to UVM(it prints junk values).
As the above table suggest, pack/unpack of queue of real numbers should be possible, as data types of both the language are satisfied.
In reply to ashwath:
The problem has nothing to do with SystemC, SystemVerilog, or UVMC. The problem is with the UVM pack/unpack macros. You would have this same problem if you tried to pack/unpack a queue of reals between two SystemVerilog UVM transactions. The pack/unpack macros do not have the intelligence to deal with reals other than as a simple singular value.