Passing a parameter to a bind entity

SystemVerilog
, ,
4

In reply to dave_59:

Thanks for pointing that out. So I take it $unit doesn’t work because it’s in reference to the bf_framer_ifc compilation unit. Before you answered, I realized that bf_framer_ifc doesn’t have my enumerated types imported, so I added the package reference to them:

bind bf_framer_ifc bf_sample_sif #(
   .SOURCE_IS_DUT ( $root.top.IS_DUT[type_pkg::BF_FRAMER] ),
   .DEST_IS_DUT   ( $root.top.IS_DUT[type_pkg::BF_TGC]    )
) raw (
   . . .
);

I thought for sure this would work but still no dice. My current solution is this monstrosity:

bind bf_framer_ifc bf_sample_sif raw (
   . . .
);

defparam fpga.bff.raw.SOURCE_IS_DUT = IS_DUT[BF_FRAMER];
defparam fpga.bff.raw.DEST_IS_DUT   = IS_DUT[BF_TGC];

Yes, this makes me feel dirty on multiple fronts; but based on what you’ve said, I can’t think of any other way.