Part selection in an array

SystemVerilog
, ,
1 
module test();
  bit[31:0] test;
  bit[6:0] rg_hit_queue[$];
  bit[6:0] rg_q_len;
  
  initial
    begin
      rg_hit_queue.push_back(2);
      rg_hit_queue.push_back(3);
      rg_q_len = rg_hit_queue.size();
      $display("%d = rg_q_len",rg_q_len);
      test = 32'hff;
      test[0] = 1;
      test[1] = 1;
      
      
      $display(" %h", test[1:0]);
      $display("%h", test[rg_q_len]);
      //$display("%h", test[(rg_q_len-1):0]);
    end
endmodule

The last display statement which is commented out gives the following error, I am unable to understand why. I want in every iteration the nth bit of test is set and in the end I want to take bitwise and (&test). How can I do this, if the above method is incorrect?
" Error-[IRIPS] Illegal range in part select
design.sv, 20
The range of the part select is illegal:
test[(rg_q_len - 1):0]

2

In reply to 100rabhh:

You need to explain better what you were trying to accomplish. It would help if you gave an example with populated data and the results you’re trying to get from it.

3

In reply to 100rabhh:

The reason that you are using non-constant for a range expression.

4

In reply to dave_59:

Hi Dave,
there is a queue which has entries depending upon a scenario(say scenario 1) being hit everytime, the max-m length of this queue could be 32. depending upon the length of the queue, we check for other scenario(say scenario 2). Now everytime scenario 2 hits I update the nth bit of a the variable “test”.

rg_q_len = rg_hit_queue.size();
for(ii=0; ii< rg_q_len; ii++) begin
test[ii] = scenario 2
once the iteration reaches the final value ii=rg_q_len,
I want to return &(test[rg_q_len-1:0]). so say rg_q_len is 5. I want &(test[4:0]).

I learnt that we cannot use constant for a range expression.

I am now using the following logic:
declaring a bit variable grant.
bit grant =1;
inside the for loop*
test[ii] = scenario 2;
grant &= test[ii];
return(grant)
this is working fine. you could suggest me any other method though.

5

In reply to cuonghle:

Thanks

6

In reply to 100rabhh:
You can use a shifted mask

return test.and() with ( item & (32'b1<<rg_q_len)-1 );