Parameterizing the Bit Widths of fields in a packed struct so that modules can infer bit width if used in port map - virtual interface - interface - compile time configured struct bit width

SystemVerilog
,
2

In reply to Ian.L.Kennedy:

The current SystemVerilog BNF does not allow any dotted “.” names in a parameter initialization. But you can get around this by using a typedef instead

interface MyInterface #(int DATA_W=0, ADDR_W=0) () ;
  typedef  logic [DATA_W-1:0]   data_t;
  ...
endinterface

module InnerTest 
  ( input wire Clock
  , input wire Reset
  , MyInterface.SNK Sink
  ) ;
 
  typedef Sink.data_t data_t;
  localparam BIT_WIDTH_SINK_DATA = $bits( data_t );
  ...
endmodule