Verification Academy
Parameterized struct in systemverilog design
SystemVerilog
array-interface-parameterized
,
packed-struct
,
SystemVerilog
abregnsbo
April 16, 2020, 10:07am
5
In reply to
dave_59
:
Shouldn’t the second
typedef
in
mod2
be
typedef p2.stage_t stage2_t
?
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