Parameterized Interfaces in Module ports!

SystemVerilog
,
1

Our dut has 2 AXI masters, 1 axi slave and 1 ahb slave.

We have parameterized both AXI and AHB interfaces. Bydefault, ADDR_WIDTH = 32, DATA_WIDTH = 32

How to use parameterized interfaces in module ports?

as like below?

module dut_wrap
(
Axi4Interface#(.ADDR_WIDTH(36),.DATA_WIDTH(64)) axi_s_0,
Axi4Interface#(.ADDR_WIDTH(36),.DATA_WIDTH(64)) axi_m_0,
Axi4Interface#(.ADDR_WIDTH(36),.DATA_WIDTH(64)) axi_m_1,
AhbSlaveInterface#(.ADDR_WIDTH(36),.DATA_WIDTH(64)) ahb_s_0
);

or

module dut_wrap #(parameter ADDR_WIDTH=36,DATA_WIDTH=64)
(
Axi4Interface axi_s_0,
Axi4Interface axi_m_0,
Axi4Interface axi_m_1,
AhbSlaveInterface ahb_s_0
);

Both getting compilation errors…

Please advise.

John

2

In reply to John Verif:

I would expect the first one to work, but you might have a problem with how you define your axi_s_0, axi_m_0, etc.

They’d have to be:


Axi4Interface#(.ADDR_WIDTH(36),.DATA_WIDTH(64)) axi_m_0

If you instantiate them with different paramters, when you try to pass them to your DUT wrapper they won’t be type compatible.

You’re going to have to show us more code.

3

In reply to Tudor Timi:

The first example is not legal; the second appears correct. Interface port absorb their parametrization from the interface instance they are connected to. There is currently no way to enforce an particular specialization other than to write code to check the parameters manually.

When you say you have compilation errors, you need to show us the errors you are getting. It would also help to see the relevant code, like ow you made the connection.

4

In reply to dave_59:

Thanks Dave. It works. yes, it is absorbing parameters from the interface instance.