Parameterized functions

SystemVerilog
,
1

I would like to know if functions can be parametrized.

For example, I would like to write a function to calculate parity of a vector. The vector input can be 32/64/128/256 bits.
Hence I would like to have a parameter that defines the width of the vector.

2

In reply to verif_learner:

IEEE 1800-2012 Section 13.8 discusses about parameterized function with the help of a wrapper class.

Basically one may have to make a parameterized class and a static function inside it. Here is an example of a static parameterized function which takes different vector widths and returns some parity. Note that we can make use of typedefs or let constructs optionally so as to keep the end user agnostic of low level function names and constructs.


module top();
  
class calc_parity #(parameter int VEC_WIDTH=8);
  static function bit calc_parity_vec(logic[VEC_WIDTH-1:0] vec);
    //...
    $display("Input is %0h",vec);
    return ^vec;
  endfunction
endclass

  let parity32bit(A)  =  calc_parity #(32)::calc_parity_vec(A);
  let parity64bit(A)  =  calc_parity #(64)::calc_parity_vec(A);
  let parity128bit(A) =  calc_parity #(128)::calc_parity_vec(A);

  initial begin
    #1;
    $display(parity128bit(128'hFFFFFFFFF));
  end
endmodule