Parameterized checker construct is not supported?

SystemVerilog
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1

Hi,

By quickly checking from LRM, it seems that parametrization of the check construct is not supported? The following is a citizen from the latest LRM.

17.2 Checker declaration

checker_declaration ::= // from A.1.2
checker checker_identifier [ ( [ checker_port_list ] ) ] ;
{ { attribute_instance } checker_or_generate_item }
endchecker [ : checker_identifier ]
checker_port_list ::= // from A.1.8
checker_port_item {, checker_port_item}
checker_port_item ::=
{ attribute_instance } [ checker_port_direction ] property_formal_type formal_port_identifier
{variable_dimension} [ = property_actual_arg ]
checker_port_direction ::=
input | output
checker_or_generate_item

I would like to know whether I have understood correctly?

Thanks.

Vaino

2

In reply to Vaino:

Correct. They are not allowed in any assertion construct: sequence, property, or checker. This is something the IEEE committee considered, but has not gotten around to implementing in the standard.

But I think you can easily work around this as these constructs are all type-less; meaning you don’t have to specify any types for the arguments. And anything you might have wanted to declare as a parameter can be passed as an argument.

3

In reply to dave_59:

Very good point that arguments of those assertion constructs can be untyped. That probably solves my problem. Basically, the reason to ask that parameterization thing was originated by generate loop construct used inside the checker to create certain amount of generate blocks declared by the parameter. But, that type-less nature of arguments makes it possible.

-Vaino