In reply to dave_59:
Ok…I will try to provide some more information without disclosing too much proprietary information. Thanks for your response.
The class is a model of an ethernet packet. I call the constructor externally and then populate the data in the task and pass the result out via the reference. The output packet will then be the input that is compared (in another instance of the interface) in the next module in the simulation. The problem is that the output packet needs to be a different type at different times in the test. Hence the need for a parameter in the interface–I want to reuse the interface task code as much as I can.
Note that the task is consuming time. I did not add the task to the class because this code is pretty specific to this particular test, and the packet model class is being used in other places where the requirements are different.
I don’t have access to the specific error message anymore (as I am not at my desk, and at any rate have fixed my code). But it was an elaboration error that said I was using the wrong class (the base class instead of the child class). I am now successfully using the technique I tried to describe above, but the solution I came up with feels kind of kludgy to me.
I think you have confirmed my suspicion that a “generic” (or “parameterization”) is not available at the function level in System Verilog. I was assuming this is possible because you can do this in C#, C++, and presumably any other modern OO language that implements generics. But maybe this is part of my problem–I suspect I am not being very “standard” in my approach.