Parameterizable assertions

SystemVerilog
,
1

Is it possible to write parameterizable properties .
As in lets say i have a property to see the clock cycle difference of 2 between two signals . Is it possible that i pass the actual signal of this property when i assert it ?

2

Hi Aman,

Yes, arguments can be passed to properties while asserting those. By this, properties can be reused.

Please find the example below:

property clk_when_not_reset(logic clk);
@(negedge clk or posedge clk)
1 |-> (!reset);
endproperty: clk_when_not_reset

// Calling the same property multiple times with different arguments
A1_clk1: assert property(clk_when_not_reset(clk1))
//$info(“A1_clk1 PASS”);
else $error(“A1_clk1 FAIL”);

A1_clk2: assert property(clk_when_not_reset(clk2))
//$info(“A1_clk2 PASS”);
else $error(“A1_clk2 FAIL”);

Regards,
Dilip