Packed array of enum data type

SystemVerilog
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1

Hi,
I was going through section for packed array in LRM-2012 and found LRM mentioning packed array are allowed to have enum as data type. Usually packed arrays are made of single bit data type only.

Anyone has any idea why enum is allowed as data type for packed arrays?

Thanks in advance,
Chander

2

In reply to Chander_M:

Any packed type can be used to make an array of a packed type. So you can use an enum type, packed struct or packed array. Note that you lose some type safety when packing an enum into another type as it becomes easier to assign an unspecified encoding into the enum.

The only exception to this packing types is using the pre-defined packed arrays — integer, int, byte, etc. This restriction is because of historical Verilog. Initially the bit-widths of these types were platform dependent The original Verilog-XL simulator had an un-implemented feature to specify the size you wanted

integer [15:0] my__short_int;

There was actually enough existing code out there to cause confusion if this was defining a packed array of 15 integers, or an integer that wanted to be 16-bits wide.

3

In reply to dave_59:

Thanks Dave for the detailed reply.