Overriding inner package define from the Testbench

SystemVerilog
1

Hi ,
Need to override some package define from the top (outside the package).

package bu ;
ifndef ABC define ABC 100
`endif
endpackage

module top ;
`define bu::ABC 111
import *::bu ;
endmodule

The above code is valid but the definition ABC still not overridden .
Is there some method to do this .
Thanks in advance.

Vlad

2

In reply to vladr:

Text define macros get processed before parsing any SystemVerilog syntax - a macro definition is not part of any scope including a package. Use parameters instead.

package bu ;
parameter ABC=100;
endpackage

module topA ;
  import bu::*;
  parameter ABC=111;
  initial $display(ABC); //displays 111
endmodule
module topB ;
  import bu::*;
  initial $display(ABC); //displays 100
endmodule