In reply to prasad_holla:
See Assertion on req and gnt signals | Verification Academy
The concept is basic:
- Tag every assertion attempt with a tag number, and then increment that tag.
- Each active assertion checks in the consequent that the tag being serviced now is the
same as its own tag before proceeding to the rest of the consequent. - Every serviced assertion, whether it passes or fails, increments the serviced tag to
allow another pending assertion to continue.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
… - SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb - Papers:
- Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy - SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy
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