Overhead of sampling a covergroup every clock cycle

SystemVerilog
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1

Hi,
I would like to know how to compute the simulation overhead of sampling a covergroup every clock cycle instead of sampling only at the required instant .

Thanks,
Omkar

2

*In reply to o-hassan:*There are too many unknowns to answer this predictably.

  1. how complicated is it to figure out when to sample if not every clock cycle?
  2. how complex are your bin expressions?
  3. Is your simulator optimized to turn off the covergroup once it reaches 100% coverage?
  4. and how long into the simulation does that take?

You may just have to try some experiments.

3

In reply to dave_59:

I just want to find out the simulation time/memory overhead when i sample at every clock edge instead of calling covergroup.sample at the right instant. You can assume the complexity to compute that instant and the complexity of bin expression is negligible.
c. That’s something I am not doing. Could you please tell me how to do that ?
d. Probably around 1000 clock cycle.

4

In reply to o-hassan:
c. This forum is not for tool specific support. Contact your vendor for tool specific help for performance guidelines.
d. I meant what percentage into the simulation. Turning off covergroups once they hit 100% coverage has more impact if that happens early in the simulation

A covergroup is just a set of counters that get allocated when you call the covergroup’s constructor. The sampling rate has no effect on the total memory consumed. But more counters actively being used means more active memory that needs to be cached.