Output to a Text file

SystemVerilog
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2

In reply to nimesh13:

You can add an initial block to open your file and a subsequent forever loop to wait for the clock edge in order to sample your signals. Something like this:


initial begin
  integer fd;
  fd= $fopen("Sample.txt", "w");

  forever begin
    @(posedge clk);
    $fwrite(fd, addr);
  end
end

Please note that an initial block is not synthesizable.