The issue which I have is connected with the output monitor module, it does not recognize the signal change.
My DUT has wfull signal, which goes to high when the memory becomes full.
And the output monitor at each wclk-clock posedge takes the value of wfull signal, puts it in transaction and sends to scoreboard.
Now when the wfull signal goes to high, than output monitor does not recognize that, and it sends the previous value of wfull to scoreboard. Please see below the picture for more details
Can you please help understand what is going here and how I can make the output monitor to catch the changed value of wfull signal?
My guess is that wfull is being driven by your DUT and is sensitive to the clock edge. When wclk goes high, the DUT will sense it’s inputs and drive wfull as a response. Even though it seems like wfull goes high at the same time that the clock does, in reality you will find that it goes high AFTER the clock edge, resulting in the wfull being sensed as 0 on the actual clock edge.
Practically(in hardware), sampling behaviour should be like that, i.e @78 DUT drives wfull equal to 1. So when it is being sampled @78, sampling value should be equal to previous value, which is 0 in your case.
Still, if there is need to get updated value of signal on the same edge on which that signal is driven, clocking block can be used, SV 1800-1200 LRM, page#311 example.
module top;
int a_in;
bit clk;
//clock
initial
begin
forever begin
#1 clk = !clk;
end
end
// clocking block
clocking cb @(posedge clk);
endclocking // cb
// sampling: It is not guaranteed a_in is update or old.
always@(posedge clk)
begin
$display("time = %t, debug: sampling on posedge clk a_in = %d", $realtime, a_in);
end
// sampling: It is guaranteed a_in is updated value.
always@(cb)
begin
$display("time = %t, debug: sampling on cb a_in = %d", $realtime, a_in);
end
// driving
always@(posedge clk)
begin
a_in = a_in +1;
$display("time = %t, debug: driving a_in = %d", $realtime, a_in);
end
// Stop simulation
initial
begin
#50 $finish;
end
endmodule // top
It seems your device is synchronized on the rising edge of clk. If you are sampling the monitor on the falling edge it should work and you are avoiding the clocking block. This is how I solve issues like this.
@prashant.kaushik I need to analyse how to add clocking block in my test environment, as it has several clocks there, I assume it needs lots of modifications in the code((
I also was thinking to add verilog #0 delay before taking the wfull value, but it also doesn’t work((
A clocking bock is a means to avoid races between TB and DUT automatically. In all my UVM projects I did so far, and this is more than 15, I never used a clocking block. In the case of DDR it might be useful to have a 2x clk. You have to investigate the problem and than make a decision. There is no general way.