Practically(in hardware), sampling behaviour should be like that, i.e @78 DUT drives wfull equal to 1. So when it is being sampled @78, sampling value should be equal to previous value, which is 0 in your case.
Still, if there is need to get updated value of signal on the same edge on which that signal is driven, clocking block can be used, SV 1800-1200 LRM, page#311 example.
module top;
int a_in;
bit clk;
//clock
initial
begin
forever begin
#1 clk = !clk;
end
end
// clocking block
clocking cb @(posedge clk);
endclocking // cb
// sampling: It is not guaranteed a_in is update or old.
always@(posedge clk)
begin
$display("time = %t, debug: sampling on posedge clk a_in = %d", $realtime, a_in);
end
// sampling: It is guaranteed a_in is updated value.
always@(cb)
begin
$display("time = %t, debug: sampling on cb a_in = %d", $realtime, a_in);
end
// driving
always@(posedge clk)
begin
a_in = a_in +1;
$display("time = %t, debug: driving a_in = %d", $realtime, a_in);
end
// Stop simulation
initial
begin
#50 $finish;
end
endmodule // top