typedef enum {NOA, TIE_H, TIE_L} sig_type_t;
sig_type_t sig_type[8];
sig_type = new();
sig_type[0] = TIE_H; // this is OK
sig_type[7] = TIE_L; // this is fine too
sig_type[8] = TIE_H; // sig_type[8] is out of range and will get NOA instead of TIE_H
If an out of range element of a dynamic array is assigned with a value for the first time, it will not get the RHS literal value in the assignment, instead it will be initialized to 0.
So here comes the problems
- Why the out of range assignment/access doesn’t trigger compile time or run time error. I’ve seen the orthodox way of widen dynamic array width while preserving old elements, which is actually create a new array to overwrite existing one, so I assume SystemVerilog automatically does this for the out of range assignment?
- If this is true, then why SystemVerilog doesn’t just take the literal value and assign it to the new element? Rather it ignore the literal and initialize the new element to 0? This can easily create buggy code.
- I only run the simulation a few times, so I am not sure if the out of range value in above example actually gets a default 0, or the 0 is just randomly pulled out of memory, and it will change from sim to sim?