Observe UVM_ERROR during Backdoor Access

UVM
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1

Hi All ,

I am referring to source code available related to Backdoor Access .
One such useful link is cluelogic_backdoor_access

However when I try to execute the code with some local changes I observe run-time error ::


UVM_ERROR: set: unable to write to hdl path (top.dut.partner.color_and_flavor)
You may not have sufficient PLI/ACC capabilites enabled for that path
UVM_ERROR: set: unable to write to hdl path (top.dut.partner.extra.sugar_free)
You may not have sufficient PLI/ACC capabilites enabled for that path
UVM_ERROR: set: unable to write to hdl path (top.dut.partner.extra.sour)
You may not have sufficient PLI/ACC capabilites enabled for that path

Link to my code :: eda_backdoor_access .
I observe the above error when running test jelly_bean_reg_test via run-time switch :: +UVM_TESTNAME=jelly_bean_reg_test

The hierarchy mentioned in the error messages top.dut.partner.color_and_flavor , top.dut.partner.extra.sugar_free and top.dut.partner.extra.sour
does exist in the actual RTL hierarchy from top .

Seek guidance for the same .

Thanks .

2

In reply to hisingh:

This is a tool related issue. You will need to refer to the tool documentation on how to enable PLI/ACC access, or try a different simulator.

3

In reply to cgales:

I added some uvm_info messages ( Link :: edaplayground ) within the body() task and re-ran the test .

On running it using other tools although I don’t observe any error message ,
I don’t observe the info messages either .

Hence I feel like it could be a RAL TB issue instead of tool related .

4

In reply to hisingh:

You don’t get error messages with the other tools because they allow PLI/ACC access.

You don’t see any uvm_info messages because the environment isn’t UVM compliant:

  • Tests and sequences have #delays. Per the UVM, the entire environment should have no #delays.
  • The test doesn’t raise/lower an objection in the run_phase(), resulting in the test exiting immediately at time 0.

There is nothing wrong with the RAL implementation.

5

In reply to cgales:

Thanks .

I was trying to debug from RAL perspective but as you pointed the issue is related to raising and dropping objections .

[ EDIT : VCS requires Compile switch -debug_access+all to to enable PLI/ACC access ]