Not able to add verilog/vhdl files to the project in questasim?

hi…
I created a new project in questa as usual… but when i tried to add verilog/vhdl files to project no window is popping up???i donno what exactly happening there… donno where the problems also???everything is fine in the past??why this unusual behavior now???
whats happening ??? is it any problem related to licence…?? we have working licence also???
can u guys please help me in this regard??
thanks in advance

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