Non-constant bit select in a force statement

SystemVerilog
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1 

              force top.DUT.submodule_top_inst.some_input[index] = 0;

The compiler does not like the use of “index”.
In my case index is a 40 bits wide.
How do I resolve this problem without writing a lot of lines of code.

Thanks!

2

In reply to new_to_uvm:

  1. Is there a way to do what you want without a force? Sometimes assigning a bit to a register is all you need.
  2. If you know how some_input normally gets its value, you can create a mask for that value
    verilog force force top.DUT.submodule_top_inst.some_input = normal_value & ~(40'b1 << index);
  3. You can use a generate loop to create 40 always blocks that waits for an event to trigger
    verilog event force_trigger; for(genvar ii;ii<40;ii++); always @(force_trigger) force top.DUT.submodule_top_inst.some_input[ii] = 0;