Non-blocking assignment

SystemVerilog
,
1 
module non_blocking();
  reg a,b,c;
  reg[2:0]d;
  initial
    begin
      $monitor($time,"a = %b b = %b c = %b d = %b",a,b,c,d);
      a <= 		1'b0;
      b <=  #10 1'b1;
      c <=  #5 	1'b0;
      d <=  #20 {a,b,c};
    end
  initial
    begin
      #100 $finish();
    end
endmodule

output of above code is:
0a = 0 b = x c = x d = xxx
5a = 0 b = x c = 0 d = xxx
10a = 0 b = 1 c = 0 d = xxx
the monitor will not display the #20 value. What is the reason, please suggest me solution?

2

Because a, b, and c are still x when the assignment to d is made at time 0.