No design being loaded during template creation

SystemVerilog
1

Edit code - EDA Playground has the template. While triggering, no design is being loaded. Not sure what to change to get all the displays to be shown

2

In reply to saikanthan7798:

You need to read the documentation on how to use EDA Playground.

3

In reply to cgales:

TOP.SV
include"interface.sv" include"common.sv"
include"trans.sv" include"gen.sv"
include"bfm.sv" include"mem.sv"
include"cov.sv" include"chkr.sv"
include"env.sv" include"memory.v"

module top;
bit clk,res;
env e=new();
memory dut(clk,res,addr,valid,wr_rd,wdata,rdata);

initial e.run();

initial
forever #5 clk=~clk; // LINE 21
initial begin

	**res=1;**                 // LINE 22
	repeat (2) @(posedge clk);
	**res=0;**                 // LINE 24
end
initial begin
	#400;
	$finish();
end

endmodule

AND.v********
module and_gate( clk, res, a, b, out);

input clk,res,a,b;
output reg out;
always@(posedge clk) begin

if(res)
	begin
		out<=0;
	end
else
begin
	out <= (a & b);
end

end

//$display(“output is %d”,out);

endmodule

************************************************************************8

ERROR

** Error: top.sv(21): (vlog-2110) Illegal reference to net “clk”.

** Error: top.sv(22): (vlog-2110) Illegal reference to net “res”.

** Error: top.sv(24): (vlog-2110) Illegal reference to net “res”.

Please advise on those errors

4

In reply to saikanthan7798:

There is nothing wrong with the code you posted. You need to post a complete example that reproduces your error.