No data flow in output interface

UVM
,
1

I am trying to run a switch project(WWW.TESTBENCH.IN - Easy Labs : UVM). As it is an old version, I made some changes to remove deprecated errors.
Modified code is in (1) - EDA Playground
Now I don’t see data flow in receiver from output interface, whereas I can see details in waveform.
can someone help me what am I doing wrong

2

In reply to vennela.adavelly:

I suggest contacting the people at testbench.in. WWW.TESTBENCH.IN

3

In reply to dave_59:

I tried mailing them but couldn’t be delivered

4

In reply to dave_59:

how do we connect interface array(interface if[4]) to any component array(Monitor mon[4]) and how do we use interface in monitor after connecting

5

In reply to vennela.adavelly:

I do not understand your complains. It works in my environment and I see the pinlevel interfaces toggeling after doing a few changes:
(1) remove the $finish in your testbench file
(2) replace the forever loops in your sequence. If there is a forever the simulation will never stop.

But I see many errors.
And there are more errors inside. You are using clocking blocks but synchronizing on the clock edge instead. This might cause more serious errors.

6

In reply to chr_sue:
thanks, I’ll work on it