No component instantiated

UVM
,
1

Hello,I’m new in UVM,M doing my first project which is a simple adder .But when I run the code it gives fatal error :
reporter [NOCOMP] ]No components instantiated. You must either instantiate at least one component before calling run_test or use run_test to do so. To run a test using run_test, use +UVM_TESTNAME or supply the test name in the argument to run_test(). Exiting simulation.
NB:the original code is taken from the book ASIC_SOC functional design verification of Mehta,Ashok B so I modified it according to my simple circuit ,Also if you notice ,it does not contain a scoreboard.sv file

DUT.sv*****************

module DUT(
	input  bit   clk,
        input  bit   rst_n,
        input  logic [1:0] a,
	input  logic [1:0] b,
	output reg   [2:0] sum);
reg[1:0] temp_out;
 //Init
always @(posedge rst_n) 
    temp_out <= 0;   
always@(posedge clk)
begin
temp_out <= a + b;
 assign sum = temp_out;
end
endmodule

lpi_seq_item.sv*

]class lpi_seq_item extends uvm_sequence_item;
 `uvm_object_utils(lpi_seq_item)
 //Data members
 rand reg a;
 rand reg b;
// rand bit cin;
  bit sum;
 //UVM methods
 function new (string name="lpi_seq_item");
 super.new (name);
 endfunction
// constraint slp_wakeup_reqs {
// (((slp_req0 || slp_req1) && (wakeup_req0 ||
//wakeup_req1)) != 1); };
endclass: lpi_seq_item
********lpi_basic_sequence.sv******
class lpi_basic_seq extends uvm_sequence #(lpi_seq_item);
 `uvm_object_utils(lpi_basic_seq)
 rand int num_of_trans;

 //UVM specific methods
 function new (string name="lpi_basic_seq");
 super.new (name);
 endfunction

 extern task body();
endclass:lpi_basic_seq

task lpi_basic_seq::body();
 lpi_seq_item seq_item;
 seq_item = lpi_seq_item::type_id::create("seq_item");
 for(int i = 0; i < num_of_trans; i++)
 begin
 `uvm_info(get_type_name(),$psprintf("in seq for count =%d", i) ,UVM_LOW)

 start_item(seq_item);
 if(!seq_item.randomize())
begin
 `uvm_error("body","Randomization failed for seq_item")
 end

 `uvm_info(get_type_name(),$psprintf("obj is a = %d, b= %d, seq_item.a, seq_item.b) ,UVM_LOW)
 finish_item(seq_item);
 end
endtask: body

lpi_sequencer.sv*****

class lpi_sequencer extends uvm_sequencer#(lpi_seq_item);
`uvm_sequencer_utils(lpi_sequencer)

 function new (string name="lpi_sequencer", uvm_component parent = null);
 super.new (name, parent);
 `uvm_update_sequence_lib
 endfunction
endclass: lpi_sequencer

lpi_driver.sv*

class lpi_driver extends uvm_driver#(lpi_seq_item);

 `uvm_component_utils(lpi_driver)
//Virtual interface
 virtual lpi_if lpi_vif;
    //event begin_record, end_record;

 lpi_seq_item seq_item;

function new (string name="lpi_driver", uvm_component parent=null);
 super.new (name, parent);
 endfunction

task run_phase(uvm_phase phase);
lpi_vif.a <= 0;
 lpi_vif.b <= 0;
 
forever
 begin
 seq_item_port.get_next_item(seq_item);
 `uvm_info(get_name(), "Sendingtransaction\n", UVM_LOW)
 seq_item.print();
 @(posedge lpi_vif.lpi_clk);
 lpi_vif.a <= seq_item.a;
 lpi_vif.b <= seq_item.b;
 seq_item_port.item_done();
 end
    seq_item_port.item_done();
    end
  endtask : run_phase
 
endclass:lpi_driver

lpi_monitor.sv**

class lpi_monitor extends uvm_monitor;
 `uvm_component_utils(lpi_monitor) 
 //Interface
 virtual lpi_if lpi_vif;
uvm_analysis_port #(lpi_seq_item) item_collected_port;
lpi_seq_item  tr;
 
 function void build_phase (uvm_phase phase);
 endfunction : build_phase

 function void connect_phase (uvm_phase phase);
 endfunction : connect_phase

 extern task run_phase (uvm_phase phase);
 endclass:lpi_monitor

 task lpi_monitor::run_phase(uvm_phase phase);
 endtask : run_phase
 
endclass

****lpi_agent.sv

class lpi_agent extends uvm_agent;
 uvm_active_passive_enum is_active;

 //Component
 lpi_driver lpi_driver_h;
 lpi_sequencer lpi_sequencer_h;
 lpi_monitor lpi_monitor_h;

 //Interface
 virtual lpi_if lpi_vif;

 `uvm_component_utils_begin(lpi_agent)
 `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_ALL_ON)
 `uvm_component_utils_end
  //uvm_analysis_port #(lpi_seq_item) item_collected_port;

 //UVM methods
 function new (string name = "lpi_agent", uvm_component parent=null);
 super.new (name, parent);
       // item_collected_port = new("item_collected_port", this);
 endfunction

function void build_phase(uvm_phase phase);
 super.build();
 //Retrieve interface from config db
 if(!(uvm_config_db #(virtual lpi_if)::get(null, "", "lpi_vif", lpi_vif)))
 begin

 `uvm_fatal(get_name(),"Can't retrieve lpi_vif from config db\n")
 end

 //Build driver and sequencer
lpi_driver_h = lpi_driver::type_id::create("lpi_driver_h",this);
lpi_sequencer_h= lpi_sequencer::type_id::create("lpi_sequencer_h",this);
`uvm_info(get_name(), "lpi agent is active now\n", UVM_LOW)
`uvm_info(get_name(), "lpi agent is_active setting finish\n", UVM_LOW)

 //Build monitor
lpi_monitor_h = lpi_monitor::type_id::create("lpi_monitor_h",this);
 endfunction:build_phase

 function void connect_phase(uvm_phase phase);
lpi_driver_h.seq_item_port.connect(lpi_sequencer_h.seq_item_export);
 lpi_driver_h.lpi_vif= this.lpi_vif;
 lpi_monitor_h.lpi_vif= this.lpi_vif;
 endfunction:connect_phase
endclass:lpi_agent
package lpi_agent_pkg;
 import uvm_pkg::*;
 `include "uvm_macros.svh"
 `include"lpi_seq_item.sv"
 `include"lpi_sequencer.sv"
 `include"lpi_driver.sv"
`include"lpi_basic_seq.sv"
 `include"lpi_monitor.sv"
 `include"lpi_agent.sv"
 `include"lpi_env.sv"
 `include"lpi_top_v_sequencer.sv"
 `include"lpi_top_env.sv"
endpackage : lpi_agent_pkg

*lpi_env.sv

class lpi_env extends uvm_env;
`uvm_component_utils(lpi_env)

    lpi_agent       lpi_agent_h;
    
    
    function new(string name="lpi_env", uvm_component parent = null);
        super.new(name, parent);
    endfunction


 extern function void build_phase(uvm_phase phase);
 extern function void connect_phase(uvm_phase phase);
endclass:lpi_env

function void lpi_env::build_phase(uvm_phase phase);
 super.build_phase(phase);
 //Build agent
lpi_agent_h= lpi_agent::type_id::create("lpi_agent_h",
this);
endfunction:build_phase

function void lpi_env::connect_phase(uvm_phase phase);
endfunction:connect_phase
endclass

lpi_if.sv

interface lpi_if(input bit lpi_clk, lpi_rstn);
 //bit is_active;
 logic [1:0]a;
 logic [1:0]b;
 logic [2:0]sum;
endinterface: lpi_if

lpi_top_v_sequencer.sv

class lpi_top_v_sequencer extends uvm_sequencer;
 `uvm_component_utils(lpi_top_v_sequencer)
 uvm_sequencer_baselpi_sqr;
function new (string name = "lpi_top_v_sequencer", uvm_component parent=null);
 super.new (name, parent);
 endfunction
endclass:lpi_top_v_sequencer

*lpi top environment.sv

class lpi_top_env extends uvm_env;
 `uvm_component_utils(lpi_top_env)
 //Global event
 uvm_event_poole_pool = uvm_event_pool::get_global_pool();

 // Instantiate environments
 lpi_top_v_sequencer lpi_top_v_sqr_h;
 lpi_env lpi_env_h;

 // Methods
 extern function new (string name="lpi_top_env", uvm_component
parent);
 extern function void build_phase(uvm_phase phase);
 extern function void connect_phase(uvm_phase phase);
 extern task run_phase(uvm_phase phase);
 endclass: lpi_top_env

function lpi_top_env::new (string name="lpi_top_env", uvm_component parent);
 super.new (name, parent);
endfunction

function void lpi_top_env::build_phase(uvm_phase phase);
 string msg = "\n";
msg = {msg, "=======================================\n"};
 msg = {msg, "*LPI TOP ENV BUILD PHASE SUMMARY*\n"};
 msg = {msg, "=======================================\n"};

 // Setting default verbosity to LOW
 if (!$test$plusargs("UVM_VERBOSITY")) begin
`uvm_info (get_name()," \nUVM_VERBOSITY not defined, using UVM_LOW \n ", UVM_LOW)
uvm_top.set_report_verbosity_level_hier(UVM_LOW);
end
super.build_phase(phase);
 lpi_env_h = lpi_env::type_id::create("lpi_env_h",this);

 //*** Build Virtual Sequencer ***
 msg = {msg, "LPI TOP V_SEQUENCER\n"};
lpi_top_v_sqr_h = lpi_top_v_sequencer::type_id::create("lpi_top_v_sqr_h", this);
   // lpi_scoreboard_h  = scoreboard::type_id::create("lpi_scoreboard_h", this);//no scoreboard
 endfunction:build_phase

//Connect Phase
function void lpi_top_env::connect_phase(uvm_phase phase);
 string msg = "\n";
 int i;
 super.connect();
 msg = {msg, "=======================================\n"};
 msg = {msg, "*LPI TOP ENV CONNECT PHASE SUMMARY*\n"};
 msg = {msg, "=======================================\n"};

 lpi_top_v_sqr_h.lpi_sqr = lpi_env_h.lpi_agent_h.lpi_sequencer_h;

 //Connect other agents sequencers
 uvm_config_db #(lpi_top_v_sequencer)::set(uvm_top, "", "lpi_top_v_sqr_h", lpi_top_v_sqr_h);
 `uvm_info(get_name(), msg, UVM_LOW)
//---------------------------------------------------------------
 endfunction:connect_phase

task lpi_top_env::run_phase(uvm_phase phase);
int i;
super.run_phase(phase);
endtask

*lpi_basic_test

//`include "lpi_env.sv"
class lpi_basic_test extends uvm_test;
 `uvm_component_utils(lpi_basic_test)
 lpi_basic_seq lpi_basic_seq_h;
 lpi_top_env m_lpi_top_env;
 virtual lpi_if lpi_vif;

 //Constructor
 function new (string name = "lpi_basic_test", uvm_component parent);
 super.new (name, parent);
 endfunction

// Build Phase
 function void build_phase(uvm_phase phase);
 super.build_phase(phase);
 m_lpi_top_env= lpi_top_env::type_id::create("m_lpi_top_env",this);

 lpi_basic_seq_h= lpi_basic_seq::type_id::create("lpi_basic_seq_h", this);

 set_config_int("m_lpi_top_env.lpi_env_h.lpi_agent_h", "is_active", UVM_ACTIVE);
 endfunction:build_phase

//RUN Phase
 task run_phase(uvm_phase phase);
 super.run_phase(phase);
 phase.raise_objection(this, "starting test_seq");
 if(!(uvm_config_db #(virtual lpi_if)::get(null, "", "lpi_vif",
lpi_vif)))
 begin
 `uvm_fatal(get_name(),"Can't retrieve lpi_vif from config db\n")
 end
 if (!lpi_basic_seq_h.randomize() with {num_of_trans == 40;})

`uvm_fatal(get_name(), "Randomization of lpi_basic_seq_h Sequence Failed \n")

 `uvm_info(get_name(),"starting seq here \n",UVM_LOW)
 wait (lpi_vif.lpi_rstn == 1);
 `uvm_info(get_name(),"reset done\n",UVM_LOW)

lpi_basic_seq_h.start(m_lpi_top_env.lpi_env_h.lpi_agent_h.lpi_sequencer_h);
`uvm_info(get_name(),"############################################## \n",UVM_LOW)
`uvm_info(get_name(),"###!!!!!! Hello World !!!!!!###\n",UVM_LOW)
 `uvm_info(get_name(),"############################################## \n",UVM_LOW)
 phase.drop_objection(this,"Finished lpi_basic_test\n");
 endtask
endclass

*lpi_testbench.sv

import uvm_pkg::*;

 `include "uvm_macros.svh"
`include "DUT.sv"
`include "lpi_if.sv"

module simpleadder_tb_top;
	import uvm_pkg::*;

	//Interface declaration
	lpi_if vif();

	//Connects the Interface to the DUT
	DUT dut(vif.clk,
			vif.reset_n,
			vif.a,
			vif.b,
			);

	initial begin
		//Registers the Interface in the configuration block so that other
		//blocks can use it
		uvm_resource_db#(virtual lpi_if)::set
			(.scope("ifs"), .name("lpi_if"), .val(vif));

		//Executes the test
		run_test();
	end

	//Variable initialization
	initial begin
		vif.clk <= 1'b1;
	end

	//Clock generation
	always
		#5 vif.clk = ~vif.clk;
endmodule
2

In reply to Imane EL:

Have you tried the suggestion in the error message?

3

In reply to dave_59:
Yes.but does not work
I have tried to write it like :
run_test(“dut”);

4

In reply to Imane EL:

The name of your test is “lpi_basic_test”

5

In reply to dave_59:

still I have same error

6

In reply to Imane EL:

I tried the code you are providing to us, but it took me a lot of time to get it running. It is so errornous. I can’t believe that it was running in your environment. I did a dirty hack to get it running. In you test you are waiting fpr your resset signal, but you do never creta e reset. Thus the simulation is stucking at runtime 0

7

In reply to Imane EL:

Hello Dave
First of all ,I would like to thank you for your response . I am a newbie to UVM and systemverilog, so please be patient with me :). I will need some spoon feeding.
I have changed the testbench and write the original version (taken from the book )and modify only what i have to modify depending on my circuit,you will find it below.still I have a fatal error but not like the previous one :
"# UVM_FATAL @ 0: reporter [INVTST] Requested test from call to run_test(lpi_basic_test) not found.
"
and with warning :
"# UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type ‘lpi_basic_test’ because it is not registered with the factory.
".
So I had to search for how to parametrize a class,then I find out that “lpi top environment.sv” should be parametrized then I can pass the arguments to “lpi_basic_test”
(please correct me if I’m wrong ).However,I don’t fully understand (I have watched your videos and read some papers)if this is the problem ,if so how to derive it and what should I derive ?
I have included this line in “lpi_top_env.sv”

class lpi_top_env extends uvm_env;
typedef uvm_component_registry #(lpi_env, "lpi_env") type_id; 
 //`uvm_component_utils(lpi_top_env)
// rest of the code

and it is constructed in “lpi_basic_test”


//....code
// Build Phase
 function void build_phase(uvm_phase phase);
 super.build_phase(phase);
 m_lpi_top_env= lpi_top_env::type_id::create("m_lpi_top_env",this);
//...code

please have a look to my code above
thank you
***lpi_testbench.sv

`include "uvm_macros.svh"
`default_nettype wire
module lpi_testbench();
import uvm_pkg::*;
reg lpi_dut_clk;
reg dut_rst_n;
//Interface
lpi_if lpi_dut_if (.lpi_clk(lpi_dut_clk));
//set lpi_if to config DB
 initial
 begin
 uvm_config_db#(virtual lpi_if)::set(null, "", "lpi_vif",lpi_dut_if);
end

lpi dut_lpi(
 .clk(lpi_dut_clk),
.rst_n(dut_rst_n),
.a(lpi_dut_if.a),
.b(lpi_dut_if.b),
.sum(lpi_dut_if.sum)
);
initial
begin
 lpi_dut_clk = 0;
dut_rst_n = 0;
#1000ns;
dut_rst_n = 1;
end
always
begin
 #10ns lpi_dut_clk = ~lpi_dut_clk;
end
initial
begin
 #0; run_test("lpi_basic_test");
end
endmodule
8

In reply to chr_sue:

OOh thank you, Actually as I mentioned before I took the code from the book ASIC_SOC functional design verification of Mehta,Ashok B .and modify it according to my circuit which is simple adder.It is not running I have fatal error.If you could possibly share your correct version,I will be so thankful ,It will help me in the future to build other circuit since I’m new to UVM .

9

In reply to Imane EL:

See here: Edit code - EDA Playground

10

In reply to chr_sue:

Thank you a lot.I have run the code in the link that you have shared ,it works but when I run in my environment (Questasim) it does not work ,it gives
UVM_WARNING @ 0: reporter [BDTYP] Cannot create a component of type ‘lpi_basic_test’ because it is not registered with the factory.

UVM_FATAL @ 0: reporter [INVTST] Requested test from call to run_test(lpi_basic_test) not found.

It is the same error when i have used the testbench from the book .please , do you have any idea how to solve it ?

11

In reply to Imane EL:

I have fixed your code with Questa 10.6b. It should not be a tool problem.
Did you pass the testname as a string to run_test like this:
run_test(“lpi_basic_test”);

12

In reply to chr_sue:

yes

13

In reply to Imane EL:

Could you please share your code through edaplayground.com.

14

In reply to chr_sue:

Thank you for answering me ,here you find the code :“(1) - EDA Playground”

15

In reply to Imane EL:

… and it is working perfectly.

16

Hi sir,
I also faced these same issue. How to you solved these ? Please explain it.

17

In reply to baladevi:

Please read the post refering to run_test above.