Articles include:
- What Do Meteorologists and Verification Technologists Have in Common?
- Using Formal Analysis to “Block and Tackle”
- Bringing Verification and Validation under One Umbrella
- The Evolution of UPF: What’s Next?
- Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features
- SVA in a UVM Class-based Environment
- The Formal Verification of Design Constraints
- OVM to UVM Migration, or “There and Back Again: A Consultant’s Tale.”
View these articles and the entire Verification Horizons February 2013 issue.