The subtitle of this book, “Essential Toolkit for Modern VLSI Design”, has definitely met its mark, and more! This is because the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation. I particularly appreciated many aspects of this book, including:
- The maturity derived from extensive years of work experiences, with successes and pitfalls.
- The organization and presentation of the subject matters, including the progression of knowledge being presented for easier absorption of the topics.
- The practical tips derived from actual usage of formal verification and from real designs.
- The various approaches, or angles of attack, in using formal verification when verifying different types of designs and situations.
- The test case examples, and progression of solutions in achieving the end goals.
In summary, I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification; I certainly learned a lot from it!
Ben Cohen,
SystemVerilog Assertions specialist