I reviewed a few sections of this book, which is now released.
From what I saw, I liked the content, and is a book that is of great value to design and verification engineers. Formal verification has gained more acceptance because of its completeness. As a believer in the value of assertions in clarifying and specifying the requirements and constraints, formal verification is a natural step in the design and verification of the design. I recommend this book.
Book info: Formal Verification, 1st Edition from Erik Seligman, Tom Schubert, M V Achutha Kiran Kumar. ISBN-9780128007273, Printbook , Release Date: 2015
The subtitle of this book, “Essential Toolkit for Modern VLSI Design”, has definitely met its mark, and more! This is because the authors thoroughly expressed their practical knowledge of this complex, and misunderstood topic, in an easy to read presentation. I particularly appreciated many aspects of this book, including:
The maturity derived from extensive years of work experiences, with successes and pitfalls.
The organization and presentation of the subject matters, including the progression of knowledge being presented for easier absorption of the topics.
The practical tips derived from actual usage of formal verification and from real designs.
The various approaches, or angles of attack, in using formal verification when verifying different types of designs and situations.
The test case examples, and progression of solutions in achieving the end goals.
In summary, I strongly recommend this book to design and verification engineers who are contemplating, or are currently using formal verification; I certainly learned a lot from it!
Ben Cohen,
SystemVerilog Assertions specialist