In reply to Dharak:
Hello!
I have faced the same problem :)
let’s say for example the interface is parametrized with parameter “sva_parameter”
and you want to wait no. of clock cycles equal to this parameter, then using ##sva_parameter will not be allowed!
then you need to make a sequence, this sequence will take the generic or the parameter as an input and it works!
Kindly check the following example:
sequence dummy_seq_1 (delay);
1 ##delay 1;
endsequence
property p1;
@(posedge clk)
(!signal_a ##2 signal_b) |-> dummy_seq_1(sva_parameter) |-> !signal_c ;
endproperty
assert property (p1)
uvm_report_info(“>> P1 << Pass”,“Check Pass”,UVM_NONE);
else
uvm_report_error(“>> P1 << Fail”,“Check Fail”,UVM_NONE);
It works :)