Need to Use Variable in Assertions ## Delay

SystemVerilog
8

In reply to mukeshkumar.saha@reliabletechsys.com:

Thank you, Good discussion,which helped me.

(rose(a), v=delay+1'b1) |-> (v>0, v=v-1'b1)[*0:] ##1 v==0 ##0 b == 1;