Need to Use Variable in Assertions ## Delay

SystemVerilog
7

In reply to aravindbhat:

Hi Ben,
I tried your code but its not working while I want to check for a error condition.

Here is the snippet code for the same,

int delay=3;
property txeidle_0;
   int x;
   @(posedge clk) ($fell(sig),x=y) |-> ((1,x=x-1) [*0:$] ##1 (x==0))  ##0 ((xp != xn) [*0:$] ##1 $rose(sig));
endproperty

Here the delay is 3, means 3 clock cycle or what ?
2.If I check for the scenario where xp != xn will assert after delay times means I want to check for the error condition.

help me out from this.