Need to Use Variable in Assertions ## Delay

SystemVerilog
41

In reply to princedavidt:

In reply to ben@SystemVerilog.us:
Is it possible to use a variable along with $past construct ?
property sig_high_check;
int high_value;
@(posedge clk)
($rose(signal_b), high_value = signal_a_reg) |-> $past($rose(signal_a),high_value);
endproperty
Throws error - variable can’t use along with $past.

The issue is not the $past, but your syntax in the use of the $past.
The syntax of the function is: [1]
$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])
More explanation from my SVA Handbook 4th Edition

Here is what I believe you wanted to express:



import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    timeunit 1ns;     timeprecision 100ps;  
	bit clk, a, b, e;  
	default clocking @(posedge clk); endclocking
	initial forever #10 clk=!clk;  
  property p; 
    bit d;
    ($rose(a), d=b) |-> $past($rose(b)) ##0 d==e;  
  endproperty 
  ap: assert property(p);                         

 initial begin 
     repeat(20) begin 
       @(posedge clk);   
       if (!randomize(a, b, e)  with 
           { a dist {1'b1:=1, 1'b0:=3};
             b dist {1'b1:=1, 1'b0:=2};

           }) `uvm_error("MYERR", "This is a randomize error")
       end 
       $stop; 
    end 
endmodule

You can simulate this at Edit code - EDA Playground

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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