In reply to ben@SystemVerilog.us:
Thanks for your reply Ben…
But I have a question on this.
I want something like…
Assertion should start with $rose(a)
Then after “Delay” value ‘b’ should be high. ‘b’ must be high only after specific “Delay”. {Delay is a variable".
I am trying to inject an error but it is not firing.
Can you please confirm that its doing same thing.
Thanks,
Dharak