Need to Use Variable in Assertions ## Delay

SystemVerilog
2

If you really want a 0 delay when “delay”==0, you could write this

property assert_check;
    int v; // variable "delay" can be >0
           // If set to "0", then no delay, 
  @(posedge clk) disable iff(disable_assertion)
  ($rose(a), v=delay+1'b1) |-> (1, v=v-1'b1)[*0:$] ##1 v==0 ##0 b == 1;
endproperty : assert_check