In reply to ben@SystemVerilog.us:
Thank you, I think you are right, I Missed that condition in generator block.
I can use this.
But I Have around 102 to 203 clocks variable. this will generate around 203 assertion for single assertion.
In reply to ben@SystemVerilog.us:
Thank you, I think you are right, I Missed that condition in generator block.
I can use this.
But I Have around 102 to 203 clocks variable. this will generate around 203 assertion for single assertion.