In reply to mpattaje:
The UVM calls the virtual method build_phase(), and that call behaves like any other SystemVerilog virtual method—it calls the most derived declaration of that virtual method.
The class uvm_component declares virtual methods for all the ~25 UVM phases and calls them unconditionally. For each instance of a uvm_component (test1 would be one such instance) the most derived version of each phase gets called. So if there is a test1::build_phase, that is what gets called. If it doesn’t, it looks for base_test::build_phase. If that doesn’t exist, the uvm_component::build_phase gets called.
If you do not call super.method_name, no other method_name in the class inheritance tree gets called automatically. So without super.build_phase in test1::build_phase, base_test::build_phase does not get called. And if base_test::build_phase does not call super.build_phase, then uvm_component::build_phase will not get called either. Note that there is no uvm_test::build_phase. The keyword super means look back in the inheritance tree for the closest override.